• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
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    • 专利摘要:
    SYSTEM AND METHOD FOR CONTROLLING ASYNCHRONUS AND INDEPENDENTLY CORE CLOCKS IN A MULTINUCLEUS CENTRAL PROCESSING UNIT. A method for controlling the core clocks in a multi-core central processing unit is disclosed and may include running a dynamic zero number clock and voltage scaling algorithm (DCVS) on a zero number core and running a first DCVS algorithm on a first core. The DCVS number zero algorithm can be operable to independently control a number zero clock frequency associated with the zero number core, and the first DCVS algorithm can be operable to independently control a first clock frequency associated with the first core.
    公开号:BR112012014160B1
    申请号:R112012014160-0
    申请日:2010-12-08
    公开日:2021-02-23
    发明作者:Bohuslav Rychlik；Ali Iranli；Brian J. Salsbery；Sumit Sur；Steven S. Thomson；Robert A. Glenn
    申请人:Qualcomm Incorporated；
    IPC主号:
    专利说明:

    RELATED REQUESTS
    [0001] The present application claims priority for provisional patent application serial number 61 / 286,967, entitled “SYSTEM AND METHOD OF ASYNCHRONOUSLY AND INDEPENDENTLY CONTROLLING CORE CLOCKS IN A MULTICORE CENTRAL PROCESSING UNIT”, filed on December 16, 2009, whose content is fully incorporated by reference. DESCRIPTION OF RELATED TECHNIQUE
    [0002] Portable computing devices (PDS) are abundant. These devices can include cell phones, portable digital assistants (PDAs), handheld game consoles, handheld computers and other portable electronic devices. In addition to the primary function of these devices, many include peripheral functions. For example, a cell phone may include the primary function of making cell phone calls and the peripheral functions of a camera, video camera, global positioning system (GPS) navigation, web browsing, sending and receiving e- mails, sending and receiving text messages, push-to-talk capabilities, etc. As the functionality of such a device increases, the computing or processing power required to support such functionality also increases. In addition, as the computing power increases, there is a greater need to effectively manage the processor, or processors, that provides the computing power.
    [0003] Therefore, what is needed is an improved method of controlling power within a multi-core CPU. BRIEF DESCRIPTION OF THE DRAWINGS
    [0004] In the figures, similar reference numbers refer to similar parts throughout the various views, unless otherwise indicated.
    [0005] Figure 1 is a front plan view of a first aspect of a portable computing device (PCD) in a closed position;
    [0006] Figure 2 is a front plan view of the first aspect of a PCD in an open position;
    [0007] Figure 3 is a block diagram of a second aspect of a PCD;
    [0008] Figure 4 is a block diagram of a processing system;
    [0009] Figure 5 is a flowchart that illustrates a first aspect of an asynchronous method and independently controls the core clocks in a multi-core device, and
    [0010] Figure 6 is a flowchart that illustrates a second aspect of a method for controlling asynchronously and independently core clocks in a multi-core device DETAILED DESCRIPTION
    [0011] The word "exemplary" is used here to mean "to serve as an example, case or illustration". Any aspect described here as "exemplary" should not necessarily be interpreted as preferred or advantageous over other aspects.
    [0012] In this description, the term "application" can also include files with executable content, such as: object code, scripts, byte code, markup language files, and paths. In addition, an "application" referred to here, may also include files that are not executable in nature, such as documents that need to be opened or other data files that need to be accessed.
    [0013] The term "content" can also include files with executable content, such as: object code, scripts, byte code, markup language files, and paths. In addition, "content" referred to herein may also include files that are not executable in nature, such as documents that may need to be opened or other data files that need to be accessed.
    [0014] As used in this description, the terms "component", "database", "module", "system" and the like are intended to refer to a computer-related entity, both hardware, firmware, a combination of hardware and software, software, or running software. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable, an execution sequence, a program, and / or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components can reside within a process and / or sequence of execution, and a component can be located on a computer and / or distributed between two or more computers. In addition, these components can run from various computer-readable media having several data structures stored therein. Components can communicate via local and / or remote processes, such as according to a signal having one or more data packets (for example, data from a component that interacts with another component of a local system , distributed system, and / or over a network such as the Internet with other systems using the signal).
    [0015] Referring initially to figure 1 and figure 2, an exemplary portable computing device (PCD) is shown and is generally designated 100. As shown, PCD 100 may include a housing 102. Housing 102 may include a portion of upper housing 104 and a lower housing portion 106. Figure 1 shows that the upper housing portion 104 may include a display 108. In a particular aspect, display 108 may be a touch sensitive display. The upper housing portion 104 may also include a trackball input device 110. In addition, as shown in figure 1, the upper housing portion 104 may include an on button 112 and an off button 114. As shown in the figure 1, the upper housing portion 104 of the PCD 100 may include a plurality of indicator lights 116 and a speaker 118. Each indicator light 116 may be a light-emitting diode (LED).
    [0016] In a particular aspect, as shown in figure 2, the upper housing portion 104 is movable with respect to the lower housing portion 106. Specifically, the upper housing portion 104 may be slidable with respect to the lower housing portion 106 As shown in figure 2, the lower housing portion 106 may include a multi-button keyboard 120. In a particular aspect, the multi-button keyboard 120 may be a standard QWERTY keyboard. The multi-button keypad 120 can be revealed when the upper housing portion 104 is moved relative to the lower housing portion 106. Figure 2 further illustrates that PCD 100 may include a reset button 122, in the lower housing portion 106.
    [0017] Referring to figure 3, an exemplary, non-limiting aspect of a portable computing device (PCD) is shown and is generally designated 320. As shown, the PCD 320 includes a 322 chip system, which includes a CPU multi-core 324. The multi-core CPU 324 may include core number zero 325, a first core 326, and an N-th core 327.
    [0018] As shown in figure 3, a display controller 328 and a touch screen controller 330 are coupled to the multi-core CPU 324. In turn, a touch-sensitive display 332 external to the 322 chip system is coupled to the controller display 328 and the touch screen controller 330.
    [0019] Figure 3 additionally indicates that a 334 video encoder, for example, a phase shift line encoder (PAL), a sequential couleur to memoire (mnemonic color) encoder (SECAM), or a committee encoder national television systems (NTSC), is coupled to the multi-core CPU 324. In addition, a video amplifier 336 is coupled to the video encoder 334 and the touch-sensitive display 332. In addition, a video port 338 is coupled to the video amplifier 336. As shown in figure 3, a universal serial bus (USB) controller 340 is coupled to the multi-core CPU 324. In addition, a USB port 342 is coupled to the USB controller 340. A memory 344 and a module card subscriber identity card (SIM) 346 can also be coupled to the multi-core CPU 324. In addition, as shown in figure 3, a digital camera 348 can be coupled to the multi-core CPU 324. In an exemplary aspect, the digital camera 348 is a camera of a steel device load-controlled (CCD) or a complementary oxide metal (CMOS) semiconductor camera.
    [0020] As additionally illustrated in figure 3, a stereo audio CODEC 350 can be coupled to the multi-core CPU 324. In addition, an audio amplifier 352 can be coupled to the stereo audio CODEC 350. In an exemplary aspect, a first speaker stereo 354 and a second stereo speaker 356 are coupled to the audio amplifier 352. Figure 3 shows that a microphone amplifier 358 can also be coupled to the stereo audio CODEC 350. In addition, a microphone 360 can be coupled to the microphone amplifier 358. In a particular aspect, a frequency modulation (FM) radio tuner 362 can be coupled to the stereo audio CODEC 350. In addition, an FM antenna 364 is coupled to the FM radio tuner 362. In addition, headphones Stereo Headphones 366 can be coupled to the Stereo Audio CODEC 350.
    [0021] Figure 3 additionally indicates that a radio frequency (RF) transceiver 368 can be coupled to the multi-core CPU 324. An RF switch 370 can be coupled to the RF transceiver 368 and to an RF antenna 372. As shown in figure 3, a keyboard 374 can be attached to the multi-core CPU 324. In addition, a set of mono headphones with a microphone 376 can be attached to the multi-core CPU 324. In addition, a vibrating device 378 can be attached to the multi-core CPU 324. Figure 3 also shows that a power supply 380 can be coupled to the 322 chip system. In a particular aspect, power supply 380 is a direct current (DC) power supply that provides power for the various components of the PCD 320 that require power. In addition, in a particular aspect, the power supply is a rechargeable DC battery or a DC power supply that is derived from an alternating current (AC) to DC transformer that is connected to an AC power source.
    [0022] Figure 3 additionally indicates that PCD 320 can also include a 388 network card, which can be used to access a data network, for example, a local area network, a personal area network, or any another network. The 388 network card can be a Bluetooth network card, a Wi-Fi network card, a personal area network (PAN) card, an ultra low power personal area network (PeANUT) technology card, or any other network card well known in the art. In addition, the network card 388 can be incorporated into a chip, that is, the network card 388 can be a complete solution on a chip, and may not be a separate network card 388.
    [0023] As shown in figure 3, the touch sensitive display 332, the video port 338, USB port 342, the camera 348, the first stereo speaker 354, the second stereo speaker 356, the microphone 360, the FM antenna 364, stereo headphones 366, RF switch 370, RF antenna 372, keyboard 374, mono headset set 376, vibrator 378, and power supply 380 are external to the 322 chip system .
    [0024] In a particular aspect, one or more of the method steps described here can be stored in memory 344 as computer program instructions. These instructions can be executed by the multi-core CPU 324 in order to execute the methods described here. In addition, the multi-core CPU 324, memory 344, or a combination thereof, can serve as a means for performing one or more of the method steps described herein, in order to control a clock associated with each CPU, or core, from the multi-core 324 CPU.
    [0025] Referring to figure 4, a processing system is shown, and is generally designated 500. In a particular aspect, processing system 500 can be incorporated into PCD 320 described above in conjunction with figure 3. As shown, the Processing system 500 may include a multi-core central processing unit (CPU) 402 and a memory 404 connected to multi-core CPU 402. Multi-core CPU 402 may include a zero number core 410, a first core 412, and an N-th core 414 The number zero core 410 may include a dynamic number zero clock and voltage sizing algorithm (DCVS) 416 running on it. The first core 412 may include a first DCVS algorithm 417 running on it. In addition, the N-th core 414 may include an N-th DCVS algorithm 418 running on it. In a particular aspect, each DCVS 416, 417, 418 algorithm can be run independently on a respective core 410, 412, 414. In addition, each DCVS 416, 417, 418 algorithm can be run completely and independently on each respective nucleus 410, 412, 414 of multiple nucleus. In addition, there is an example of a DCVS algorithm 416, 417, 418 per core 410, 412, 414 and DCVS algorithm 416, 417, 418 can monitor and control the core clock 410, 412, 414 on which it runs . Each DCVS algorithm 416, 417, 418 can independently define a different clock frequency for each core 410, 412, 414.
    [0026] In a particular aspect, each DCVS 416, 417, 418 algorithm can be identical and each one can monitor the same parameter, for example, idle time, workload, etc. In another aspect, each DCVS algorithm 416, 417, 418 can be identical, but each can monitor a different parameter. In another aspect, each DCVS algorithm 416, 417, 418 can be different, but each can monitor the same parameter. In yet another aspect, each DCVS algorithm 416, 417, 418 can be different and each can monitor a different parameter.
    [0027] In another aspect, the DCVS algorithm number zero 416 can use idle information from nucleus number zero 410, first nucleus 412, N-th nucleus 414, or any combination of these. The first DCVS algorithm 417 can use idle information from nucleus number zero 410, first nucleus 412, N-th nucleus 414, or any combination of these. In addition, the N-th DCVS algorithm 418 can use idle information from nucleus number zero 410, first nucleus 412, N-th nucleus 414, or any combination of these.
    [0028] In addition, as illustrated, memory 404 may include an operating system 420 stored therein. Operating system 420 may include programmer 422 and programmer 422 may include a first run queue 424, a second run queue 426, and an Nth run queue 428. Memory 404 may also include a first application 430, a second application 432, and an N-th application 434 stored there.
    [0029] In a particular aspect, applications 430, 432, 434 can send one or more jobs 436 to operating system 420 to be processed on core 410, 412, 414 within the multi-core CPU 402. Jobs 436 can be processed, or performed, as single tasks, sequences, or a combination of these. In addition, programmer 422 can program tasks, sequences, or a combination of them to run within the multi-core CPU 402. In addition, programmer 422 can place tasks, sequences, or a combination of them in execution queues 424, 426, 428. Cores 410, 412, 414 can retrieve tasks, sequences, or a combination of them from execution queues 424, 426, 428 as indicated, for example, by operating system 420 for processing, or executing that task and sequences in cores 410, 412, 414.
    [0030] Figure 4 also shows that memory 404 may include a parallelism monitor 440 stored therein. The parallelism monitor 440 can be connected to the operating system 420 and the multi-core CPU 402. Specifically, the parallelism monitor 440 can be connected to the programmer 422 within the operating system 420. As described here, the parallelism monitor 440 can monitor the workload in cores 410, 412, 414 and the parallelism monitor 440 can control the power for cores 410, 412, 414.
    [0031] Referring to figure 5, a first aspect of an asynchronous method and independently controlling the cores in a multi-core device is shown and is generally designated 500. Method 500 can start at block 502, with an em loop that when the device is turned on, the following steps can be performed.
    [0032] In block 510, a DCVS algorithm number zero can be executed in a nucleus number zero. Then, in block 512, a number zero clock associated with the number zero core can be monitored. In addition, in block 514, an idle time associated with core number zero can be monitored. In block 516, the clock frequency of the number zero clock associated with the number zero core can be varied based on the number zero core idle time. In addition, in block 518, the voltage of the number zero core can be varied based on the idle time of the number zero core.
    [0033] Moving to decision 519, the power controller can determine whether the device is turned off. If the device is turned off, the method may end. Otherwise, if the device remains on, method 500 can return to a location shortly after performing step 502 and method 500 can continue as described.
    [0034] Continuing with the description of method 500, in block 520, a first DCVS algorithm can be executed in a first core. Then, in block 522, a first clock associated with the first core can be monitored. In addition, in block 524, an idle time associated with the first core can be monitored. In block 526, the clock frequency of the first clock associated with the first core can be varied based on the idle time of the first core. In addition, in block 528, the voltage of the first core can be varied based on the idle time of the first core. Thereafter, method 500 can continue to decision 519 and continue as described here.
    [0035] In block 530, an N-th DCVS algorithm can be executed in an N-th nucleus. Then, in block 532, an N-th clock associated with the N-th core can be monitored. In addition, at block 534, an idle time associated with the Nth nucleus can be monitored. In block 536, the clock frequency of the N-th clock associated with the N-th nucleus can be varied based on the idle time of the N-th nucleus. In addition, in block 538, the voltage of the first core can be varied based on the idle time of the first core. Thereafter, method 500 can continue to decision 519 and continue as described here.
    [0036] It can be appreciated that steps 510 to 518, steps 520 to steps 528 and steps 530 to 538 can be performed in parallel. As such, independent asynchronous clock control can be provided with a clock associated with each core.
    [0037] Referring to figure 6, a second aspect of an asynchronous method and independently controlling the cores in a multi-core device is shown and is generally designated 600. Method 600 can start at block 602, with an em loop that when the device is turned on, the following steps can be performed.
    [0038] In block 610, a DCVS algorithm number zero can be executed in a nucleus number zero. Then, in block 612, a number zero clock associated with the number zero core can be monitored. In addition, in block 614, a workload associated with core number zero can be monitored. In block 616, the clock frequency of the number zero clock associated with the number zero core can be varied depending on the workload of the number zero core. In addition, in block 618, the voltage of the number zero core can be varied depending on the workload of the number zero core.
    [0039] Moving to decision 619, the power controller can determine whether the device is turned off. If the device is turned off, the method may end. Otherwise, if the device remains on, method 600 can return to a location shortly after performing step 602 and method 600 can continue as described.
    [0040] Continuing with the description of method 600, in block 620, a first DCVS algorithm can be executed in a first core. Then, in block 622, a first clock associated with the first core can be monitored. In addition, in block 624, a workload associated with the first core can be monitored. In block 626, the clock frequency of the first clock associated with the first core can be varied depending on the workload of the first core. In addition, in block 628, the voltage of the first core can be varied depending on the workload of the first core. Thereafter, method 600 can continue to decision 619 and continue as described here.
    [0041] In block 630, an N-th DCVS algorithm can be executed in an N-th nucleus. Then, in block 632, an N-th clock associated with the N-th core can be monitored. In addition, in block 634, a workload associated with the Nth nucleus can be monitored. In block 636, the clock frequency of the N-th clock associated with the N-th core can be varied depending on the workload of the N-th core. In addition, in block 638, the voltage of the first core can be varied depending on the workload of the first core. Thereafter, method 600 can continue to decision 619 and continue as described here.
    [0042] It can be appreciated that steps 610 to 618, steps 620 to 628 and steps 630 to 638 can be performed in parallel. As such, independent asynchronous clock control can be provided with a clock associated with each core.
    [0043] It should be understood that the method steps described here do not necessarily have to be performed in the order as described. In addition, words like "after", "next", "next", etc. they are not intended to limit the order of the stages. These words are simply used to guide the reader through the description of the steps of the method. In addition, the methods described here are described as executable on a portable computing device (PCD). The PCD can be a mobile phone device, a portable digital assistant device, a smartbook computing device, a netbook computing device, a portable computing device, a desktop computing device, or a combination of these.
    [0044] The system and methods described here provide completely independent DCVS algorithms (a.k.a DVFS) that can be executed completely independently on the multiple cores. There is one instance of a DCVS algorithm per core, and each monitors and controls the clock for that core only. Multiple algorithms are allowed to independently define different clock frequencies for multiple cores.
    [0045] In a particular aspect, each DCVS algorithm instance can monitor the percentage of downtime spent in each core. The core idle time can be obtained from the operating system or through special external hardware counters, such as a system profile and diagnostic monitor (SPDM). In another aspect, each DCVS algorithm can monitor a workload characteristic, such as a memory task without limitation and independently adjust frequency based on the characteristics of the different tasks running in each core.
    [0046] In one or more exemplary aspects, the functions described can be implemented in hardware, software, firmware, or any combination of these. If implemented in software, functions can be stored in or transmitted through as one or more instructions or code in a computer program product such as a machine-readable medium, that is, a computer-readable medium. Computer-readable media includes both computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one place to another. The storage media can be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used. used to transport or store the desired program code in the form of instructions or data structures and which can be accessed by a computer. In addition, any connection is properly called a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio and micro- waves, then coaxial cable, fiber optic cable, twisted pair, DSL or wireless technologies such as infrared, radio, and micro wave are included in the media definition. Disk and floppy disk, as used here, includes compact disk (CD), laser disk, optical disk, digital versatile disk (DVD), floppy disk and blu-ray disks where floppy disks normally reproduce data magnetically, while disks reproduce data optically with lasers. The combinations of the above must also be included within the scope of computer-readable media.
    [0047] Although the selected aspects have been illustrated and described in detail, it will be understood that various substitutions and changes can be made to them without departing from the spirit and scope of the present invention, as defined by the claims that follow.
    权利要求:
    Claims (3)
    [0001]
    1. Method for controlling core clocks in a multi-core central processing unit (402), the method characterized by the fact that it comprises: executing a dynamic number zero clock and voltage dimensioning algorithm (416), on a number zero core (410) to monitor a number zero core timeout and vary a core number zero clock frequency based on the monitored timeout; and executing a first DCVS algorithm (417) on a first core (412) to monitor a memory without limiting a first core workload and varying a clock frequency of the first core (412) based on the memory without monitored limitation of the workload, where the DCVS algorithm number zero (416) is operable to independently control the clock frequency associated with the core number zero (410) and the first DCVS algorithm (417) is operable to independently control the frequency of clock associated with the first core (412) and in which the DCVS algorithm number zero (416) and the first DCVS algorithm (417) are completely independent of each other.
    [0002]
    2. Wireless device characterized by the fact that it comprises: means to execute a dynamic number zero clock and voltage sizing algorithm (416), DCVS, on a number zero core (410) to monitor a number zero core timeout and varying a core clock frequency number zero based on the monitored waiting time; and means for executing a first DCVS algorithm (417) on a first core (412) to monitor a memory without limiting a workload of the first core and varying a clock frequency of the first core (412) based on the memory without monitored workload limitation, where the DCVS algorithm number zero (416) is operable to independently control the clock frequency associated with the core number zero (410) and the first DCVS algorithm (417) is operable to control independently the clock frequency associated with the first core (412) and where the DCVS algorithm number zero (416) and the first DCVS algorithm (417) are completely independent of each other.
    [0003]
    3. Computer-readable memory characterized by the fact that it comprises instructions stored therein, the instructions being executable by a computer to perform the steps of the method as defined in claim 1.
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    法律状态:
    2019-01-08| B06F| Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]|
    2019-08-06| B06U| Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]|
    2020-05-19| B06A| Patent application procedure suspended [chapter 6.1 patent gazette]|
    2020-07-28| B06I| Publication of requirement cancelled [chapter 6.9 patent gazette]|Free format text: ANULADA A PUBLICACAO CODIGO 6.1 NA RPI NO 2576 DE 19/05/2020 POR TER SIDO INDEVIDA. |
    2020-11-03| B09A| Decision: intention to grant [chapter 9.1 patent gazette]|
    2021-02-17| B09X| Republication of the decision to grant [chapter 9.1.3 patent gazette]|
    2021-02-23| B16A| Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]|Free format text: PRAZO DE VALIDADE: 10 (DEZ) ANOS CONTADOS A PARTIR DE 23/02/2021, OBSERVADAS AS CONDICOES LEGAIS. |
    优先权:
    申请号 | 申请日 | 专利标题
    US28696709P| true| 2009-12-16|2009-12-16|
    US61/286,967|2009-12-16|
    US12/944,321|US8689037B2|2009-12-16|2010-11-11|System and method for asynchronously and independently controlling core clocks in a multicore central processing unit|
    US12/944,321|2010-11-11|
    PCT/US2010/059535|WO2011084328A1|2009-12-16|2010-12-08|System and method for asynchronously and independently controlling core clocks in a multicore central processing unit|
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